Port mapping in module instantiation can be done in two different ways: Port mapping by order Port mapping by name In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows…
Category: DHD
Digital Hardware Design
Module Instantiation in Verilog
A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating…
Ports in Verilog Module
Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All…
Module Definition in Verilog
A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but…
State Equivalence & Minimization Part – 2
The states which are equivalent, are redundant. Because by looking at the output, we can not even figure out in which state the machine is in. So, if there are two equivalent states then there is no point of using…
State Equivalence & Minimization Part – 1
Sometimes a state diagram constructed for a finite state machine contains redundant states, i.e. states whose function can be accomplished by other states. The number of memory elements required for the realization of a machine is directly related to the…
Circuit Design of Parity Generator
This post illustrates the circuit design of Even Parity Generator. State Machine diagram for the same Parity Generator has been shown below. Click here to realize how we reach to the following state transition diagram. Click here to learn the step…
State Machine Diagram for Parity Generator
Parity generator can be of two types: (i) Even Parity Generator (ii) Odd Parity Generator In this post we will derive the state machine for an even parity generator. Consider input “I” is a stream of binary bits. When an…
Circuit Design of a Sequence Detector
This post illustrates the circuit design of Sequence Detector for the pattern “1101”. State Machine diagram for the same Sequence Detector has been shown below. Click here to realize how we reach to the following state transition diagram. Click here to…
State Machine Diagram for Pattern Recognition / Sequence Detector
Sequence Detector is a digital system which can detect/recognize a specified pattern from a stream of input bits. Let’s say the Sequence Detector is designed to recognize a pattern “1101”. Consider input “X” is a stream of binary bits. When…