Port Mapping for Module Instantiation in Verilog

Port mapping in module instantiation can be done in two different ways:

• Port mapping by order
• Port mapping by name

In this post, we would take one example to understand both types of port mapping in detail.

The above Figure shows an example for module instantiation. Figure shows module “SYNCHRO” which consists of 2 ‘D’ flip-flops and are connected in serial fashion. Module “SYNCHRO” has 2 input ports “ASYNC” and “CLOCK” and 1 output port “SYNC”.

Verilog Programming for DFF instantiated in the SYNCHRO module:

module DFF (Q, D, CLK);
  input D, CLK;
  output reg Q;
  always @ (posedge CLK)
    Q <= D;
endmodule

MODULE PORT MAPPING BY ORDER

module SYNCHRO (ASYNC,SYNC,CLOCK);
  input ASYNC;
  input CLOCK;
  output SYNC;
  
  wire C1_ASYNC;
  
  DFF DFF1 (C1_ASYNC, ASYNC, CLOCK);
  DFF DFF2 (SYNC, C1_ASYNC, CLOCK);

  //Check what happens when you would replace the above two lines with the below two lines
  //DFF DFF1 (ASYNC, C1_ASYNC, CLOCK);
  //DFF DFF2 (SYNC, C1_ASYNC, CLOCK);

endmodule

Here first instance name of ‘D’ flip-flop is “DFF1” and second instance name is “DFF2”. In this module ports are connected by order. Order of ports in instantiation of DFF1 and DFF2 is same as order of ports in DFF. If the number of ports increased, then it is very difficult to do “module ports connection by order”.

MODULE PORT MAPPING BY NAME

 
Module SYNCHRO (ASYNC, SYNC, CLOCK); 
  input ASYNC;
  input CLOCK;
  output SYNC;

  wire C1_ASYNC;

  DFF DFF1 (.D (ASYNC), .CLK (CLOCK), .Q (C1_ASYNC));
  DFF DFF2 (.D (C1_ASYNC), .Q (SYNC), .CLK (CLOCK)); 

endmodule

In this module, ports are connected by Name. Order of ports in instantiation of DFF1 and DFF2 is different from order of ports in DFF. In this ‘.’ is used to represent port name followed by associated port name in small brackets i.e. “()”. Advantage of using “port connection by name” is, it is easy to port map for large number of ports in a design.

Tip: Always connect ports by name to avoid any error.