In the part-1 of ESD we learnt through of ESD testing and its importance. ICs are susceptible to ESD event as they consist of components that are very sensitive to excess current and voltage. ESD even can occur at any point in time during IC assembly and packaging, part handling or system assembly. Important point to note here is that ESD event does not even require the chip to be powered up. There are standards and models developed to make sure that all the ICs go through proper ESD design and testing. A generic model of ESD testing consist of 5 things,
- Charged capacitor representing the ESD event (Vesd)
- A switch
- Series Inductance
- Series internal resistance
- Electronic component (IC)
Here is the diagram for reference,
Source resistance should be as high as possible to lower the magnitude of current under an ESD event.
Generally ESD is modelled using three different methods named as Human Body Model, Machine Model and Charged Device Model. These are different ways to emulate and ESD event with different parameter values. Let’s have a look,
- Human body model (HBM): As the name also suggests, this model represents of an ESD event between a human body and an electronic component. HBM model helps to simulate stress level developed by electronic component through human touch discharging the static charge through device to ground. The typical model values used for HBM models are, R_SRC = 2000 Ohms, CESD = 100pF, L = 0 (Negligible inductance for human body). With these parameters if Vesd is 3KV (since wiki says Synthetic fabrics and friction can charge a human body to about 3 kV) then the maximum current Imax will be a whopping 1.5Amps.
- Machine Model (MM): This model represents the scenario when a machine or an automatic handling unit touches the IC. This is highly likely when there is a metal to metal contact during production.The typical model parameter values used for Machine Model are, R_SRC = 100 Ohms, CESD = 200PF, L = 0.5nH (this was negligible in Human Body Model but It is no longer the case with Machine Model.)With these parameter values if VESD = 5KV then Imax will be 5Amps. Also with inductance into picture we will see some ringing in the current. Here is the waveform,Fortunately, Machine model is not used very often now a days since fabrication is all automated and ESD prune.
- Charged Device Mode (CDM): this model assumes the IC itself getting changed and then touching any ground plane. The CDM also addresses the possibility of charge residing in the package and later discharge through a pin which is grounded. Here, R_SRC = 10-15Ohms, CESD = Cpackage, L = 0.5nH. Hence if VESD = 500V then IMAX = 10Amps.
CDM is very fast as can be seen in the waveform as well and it also has the highest peak current of all the models which can also be attributed to low source resistance.
Comparison of the HBM, MM and CDM current waveforms.
- Peak current in CDM model is much higher.
- Dynamics of CDM is much quicker.
- Both MM and CDM has inductive behavior (negative peaks).
There are one more model which is very frequently talked about named as System Level Model (IEC-61000). This is a system level model which assumes IC to be mounted on PCB and requires system to be powered up and operating. This is similar to component level models but at much higher stress levels. The typical requirement is 4KV – 8KV.
This was the introduction to various ESD models and their comparison. Stay tuned for more updates!!!