Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. They are procedural assignments always used in a procedural block…
Tag: Verilog
Ports in Verilog Module
Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All…
Module Definition in Verilog
A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but…
Synopsys – Interview Questions – based on Synthesis and Simulation
This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself…
Training Experience – Mentor Graphics Higher Education Program
Hello Everyone! This is my training experience, I had at Mentor Graphics, Noida (Higher Education Program) which is conducted annually for pre-final year B.Tech and M.Tech students. It is a two month training program that starts in June and lasts…
Case and Conditional Statements Synthesis CAUTION !!!
Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by…
Interview Experience – Tech Mahindra – VLSI Domain (Off Campus – Telephonic)
I got an Interview call from Tech Mahindra VLSI Dept, and I am sharing my Interview Experience here. The Interview was telephonic and and was about 55 minutes long. They asked for core technical questions related to HDL (Hardware Description…
Interview Experience – Silicon Interfaces – for Trainee VLSI Design (Off Campus)
Hello everyone !!! This is my interview experience for the post of Trainee VLSI design at Silicon Interfaces, A software and VLSI Design centre. This post also presents my thoughts towards “What should be done to get noticed by VLSI…
Power Analysis in XILINX Xpower Analyzer
These are some simple steps which can be used to do the power analysis of a design using Xpower Analyzer which comes readily available in the ISE free web pack. ## Make sure your circuit can be synthesized. Then under…
Verilog vs VHDL
Verilog and VHDL are Hardware Description languages (HDL) that are used to describe the behavior and structure of electronic systems. HDL languages are different form software language like ‘C’, as they use concurrency constructs to simulate circuit behavior. HDL includes…