This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself or herself and then discuss these in the forum.
1. How a latch gets inferred in RTL design?
Ans. A latch gets inferred in the RTL design:-
- When there is no “else / default” statement in the “if / case” statements; in short if all possibilities of the conditions are not covered.
- When all the outputs reg are not assigned the values in every condition of the “if / case” statement and some are left out, on the left out signals a latch gets inferred.
2. Does a latch get inferred when there is no else statement but multiple ifs covering whole functionality?
Ans. Conceptually no latch should be inferred but sometimes the synthesis tools are not intelligent enough and they might infer a latch. In order to avoid that, the safest way is to use an “else / default” statement in “if / case” respectively.
3. If there is an asynchronous feedback loop what is the problem?
Ans. If there is an asynchronous loop in the design the circuit becomes oscillatory or it may reach a stable state where it might get hung and it could not get out.
4. If an oscillatory circuit is there; what happens during (a) RTL Synthesis (b) Simulation?
Ans. (a) During the RTL synthesis, the synthesis tool will give a warning during synthesis about the combinatorial feedback loop.
(b) During the simulation the simulation will get stopped saying the Iteration limit reached.
5. Where can we use Linting tools ? Can we use them to debug syntax?
Ans. Linting tools are used to evaluate the design for the synthesizability of the design. These tools are use to check for potential mismatches between simulation and synthesis. No they are not used to check the syntax.
6. What can be done to break the combinational loop?
Ans. By adding synchronous elements in the path. If it is really needed and if the design permits then by adding the buffers in the path.
7. why we use B.A (Blocking Assignments) and N.B.A (Non Blocking Assignments)?
Ans. B.A are used to model combinatorial logic as the value is of continuous assignment and doesn’t depend on the previous value, while N.B.A are used to model sequential circuits as the previous value is needed to propagate.
8. What will be the output of the following code?
always ( * ) begin a = b + d; a = c + b; end
Ans. This is actually a race condition and the tool will take the last assignment on “a”.
9. Is there a latch in the following code? What if the “sel” value is “X”. What will be the simulation result?
always @ ( en ) begin dout = 0 case ( sel ) 0: dout = in ; end
Ans. No There is no Latch as dout=0 before the case statement will be executed. Even if the “sel” value is “X”, no latch would be formed as “dout” has been already initialized to “0”.
10. Is there a latch in the following code? What if the “sel” value is “X”. What will be the simulation result?
always @ ( en ) begin dout = 0 case ( sel ) 0: dout = in ; default : dout = 1; end
Ans. No There is no latch as the default statement is present and the output will be govern by the case statement.
11. If no parameters in the always sensitivity list, how the always block executes?
Ans. It will repeat itself like a forever loop but the performance will degrade.
12. Tell the scenarios where synthesis error occurs.
Ans. A synthesis error can occur in the following scenarios:
- When there is multiple assignments on the same signal in two different blocks, “a multiple driver found” message will come.
- When there is mixture of asynchronous reset with some other signal and that signal is not used in the sensitivity list; basically mixing of multiple edges and synchronous and asynchronous elements are not allowed.
- No element in the always block sensitivity list.
- Mixing of B.A and N.B.A on the same signal in two different conditional statements.
- If reg datatypes are used in assign statements, etc.
13. Is the following code synthesizable?
always @ (posedge clk1 or negedge clk2) begin if (!clk2) dout <= 0; else dout<= din; end
Ans. Yes it is synthesizable try to read clk2 as active low reset.
14. Are the following codes are synthesizable ? Is there any difference in the synthesis result of (i) and (ii)?
always @ (posedge clk1 or negedge clk2) begin if (!clk2 && a) dout <= 0; else dout<= din; end
always @ (posedge clk1 or negedge rst) begin if (!rst && a) dout <= 0; else dout<= din; end
Ans. Both are not synthesizable as there is a mixing of asynchronous and synchronous element in the if condition.