VLSI Transistor Basics Interview Question Bank-1

This part of the Interview Question Bank deals with the general transistor level questions asked in various VLSI companies

Q1. If you connect the input of an inverter to its output where will the output gets settled?

Ans. The output will settle at the logical threshold of the inverter ideally at VDD/2.

Q2. The Vt of the transistor increases or decreases with the temperature.

Ans. The Vt of the the transistor decreases with temperature?

Q3. According to the saturation current equation the current through the transistor increases as Vt of the transistor decreases but it is not the case in practical situation, the reason is ?

Ans. The reason is the mobility of the charge carriers as it is the more prominent factor in the ON current equation and it decreases with the temperature.

Q4. What is channel length modulation and how it occurs?

Ans. Channel length modulation is the shortening of the channel length after Pinch off occurs, this causes the saturation current to increase linearly with Vds. This occurs due to the widening of the depletion region between drain to bulk region, primarily in the channel.

Q5. What are short channel effects, is channel length modulation also a short channel effect?

Ans. In short channel technologies, vertical electric field loses its complete control over the channel. That is gate loses its control over the channel as the horizontal electric field starts interfering with the channel formation. The most prominent effects are subthreshold leakage, velocity saturation. No, channel length modulation is not a short channel effect as it occurs after pinch off point, while short channel effects are mostly pre or during channel formation.

Q6. How does a Vt of transistor varies with temperature and doping and why?

Ans. The Vt of the transistor decreases as the temperature increases as minority carrier concentration increases, while Vt of the transistor decreases with increased doping as more majority carriers needs to be pushed into the bulk to create the depletion region before channel formation.

Q7. The value of the capacitance between gate to bulk for an NMOS transistor is maximum in which region of the MOS?

Ans. The gate to bulk capacitance is maximum for the cutoff region of the transistor.

Q8. Considering a 3 terminal NMOS device if a supply of Vdd is connected to the gate of a NOMS having Vt as the threshold value, and the supply voltage of Vdd is connected to either of the remaining terminal, In which of the region does the NMOS is in, and what is the output voltage at the remaining terminal?

Ans. The transistor being an NMOS works in saturation region, and being an NMOS its weak pull up, the output voltage will be Vdd-Vt.

Q9. Considering the question above if we connect another NMOS with its drain connected to the output of the previous NMOS and gate being connected to Vdd, then in which region does this NMOS operates in and what is the output voltage?

Ans. The transistor works in saturation region, the output voltage will be Vdd-Vt. The first transistor is connected to Vdd which make it’s Vds as Vdd -(Vdd-Vt) which is greater than Vgs-Vt, for the second transistor it can pass the voltage level up to which Vgs = Vt, this means it can also pass the full Vdd – Vt potential which is at its drain, also here Vds = Vgs – Vt, so it also works in saturation region.

Q10. If the voltage Vsb that is source to bulk voltage difference is increased in an NMOS how does Vt varies and why?

Ans. The Vt of the transistor increases, as the depletion region around the p-n junction increases and it takes more gate voltage to offset that charge.

Cisco Systems Interview Question Bank – Part 1

Continuing with our series of Question Banks of various core companies of ECE, we have now collected the following questions asked in interviews of Cisco Systems. These questions will help you prepare for on-campus and off-campus interviews of Cisco. Let’s take a look at them…

Q : What is gateway?

A : Gateway is a piece of networking hardware that acts as an entry point to another network. It is used for interfacing with another network that uses different protocols.

Q : What do you mean by a default gateway? Give a real-life example.

A : It is a device that passes traffic from the local subnet to devices on other subnets, often used to connect a local network to the Internet (even though internal gateways for local networks also exist). In a home network with a broadband router sharing the Internet connection, the home router serves as the default gateway.

Q : Explain VLAN.

A : VLAN (Virtual LAN) is a group of flexible logical devices (instead of physical ones) connected to one or more LANs (Local Area Networks) and are configured to communicate just like they were attached to the same wire but are actually located on a number of different LAN segments.

Q : What is Trunk port? Why is it needed?

A : Trunk port is a kind of port that is responsible for carrying traffic for all the VLANs that are accessible by a specific switch by a process called trunking. Trunk ports mark frames with uniquely identifying tags (either 802.1Q tags or ISL (Inter Switch Link) tags) as they move between switches. Thus, every single frame can be directed to its designated VLAN.

Q : What do mean by NAT?

A : NAT (Network Address Translation) is the process of re-mapping an IP address space into another one by making modifications in the network address information in IP (Internet Protocol) datagram packet headers while they are moving across a traffic routing device.

Q : What is pipelining?

A : Pipelining is the process of en-queuing the next process to be executed while the current process is still under execution.

Q : At which OSI layer does the retransmission of packets take place?

A : The retransmission of packets takes place in the Network layer of OSI model.

(Continued to Part 2…)

Gautam Vashisht

MEMS Design Contest 2018 in association with Cadence Academic Network, X-FAB, Coventor, and Reutlingen University

A world wide MEMS (Microelectromechanical systems) Design Contest is going to be organized in 2017-18. The Cadence Academic Network, X-FAB, Coventor, and Reutlingen University have been teamed up to build this platform which would provide the opportunity to showcase the innovative ideas. The contest is all about design and build the best MEMS and mixed-signal designs.

Important Timeline

December 31, 2016: End of application period and submission of proposal

March 1, 2017: 

  • Acceptance notification
  • PDK and Software delivery
  • Design phase start

December 31, 2017: Design submission deadline

February 28, 2017: Announcement of Finalists

CDNLive EMEA 2018: Award Ceremony

To know more about the contest please click here. Register for the contest clicking here.

India Innovation Challenge with support from Texas Instruments India, DST and IIMB

Texas Instruments Inc. in collaboration with Department of Science and Technology(DST) proudly announce the ‘DST & Texas Instruments Inc. India Innovation Challenge Design Contest 2016′, Anchored by the Indian Institute of Management (IIM), Bangalore and supported by MyGov. The contest is open for all students pursuing B.E./B.Tech,M.E./M.Tech & Ph.D from Indian engineering colleges.

This challenge would provide a fantastic platform to the students to showcase their innovative idea. This contest is for students from Indian engineering colleges who have a dream to create something new, aspire to make a difference and contribute to India’s success towards becoming an innovation hub. Leaders from Industry, Academia and Govt. of India would put their hands together to make your idea an reality.

Texas Instrument would provide the technical mentorship and resources for innovative product design.

IIM Bangalore would provide its smart and experienced brains for mentorship in incubating the startup.

Department of Science and Technology, Govt. of India would provide the seed funding to lunch the product.

Fund of INR 1.5Crores will be invested on Product Development and Seed Fund of INR 2Crores to be distributed among top teams.

  • Chairman’s Award  INR 7,00,000
  • First Runner Up INR 3,50,000
  • Second Runner-Up Award INR 1,50,000

Last Date of Submission of Proposal: September 30, 2016




Assembly Language Program for Unpacking the Packed BCD number in 8085 Microprocessor

Binary coded decimal (BCD) is a way to express each of the decimal digits with a binary code. This means that each decimal digit, 0 through 9, is represented by a binary code of four bits.

Eg: 98 => 10011000

Unpacking the BCD number is separating each BCD digit.

Eg: 98 can be separated as 09 and 08. So we can say 10011000 [98] is packed and 00001001 [09] & 00001000 [08] are unpacked.

You might like to go through Step by step Process to add two packed BCD Numbers

Assembly language program to unpack the packed BCD number

// Manually store the packed BCD number [eg: 98 in this case] in the memory locations 3000H
// Store the result i.e, the unpacked numbers in the memory locations 3001H and 3002H
// For this Example result will be 09 and 08
// 3000<-09, 3001<-08

#ORG 0000H
#BEGIN 0000H

    LDA 3000H  //Get the packed BCD number from the memory
    MOV B,A
    MVI C,04
    ANI F0     // A = 90H

L1: RRC        // Need to be rotated right for 4 times to get A = 09H
    DCR C
    JNZ L1

    STA 3001
    MOV A,B
    ANI 0F     // A = 08H
    STA 3002

#ORG 3000H
#DB 98H

Now when you would run the program it would give you the memory locations with the following values:

Unpacking BCD Number

Note: The above Hex codes have been assembled and simulated on Jubin’s 8085 Simulator.

Hope the post would help you. If any doubt, please mention the same in the comment section, we would revert back to you.