This part of the Interview Question Bank deals with the general transistor level questions asked in various VLSI companies
Q1. If you connect the input of an inverter to its output where will the output gets settled?
Ans. The output will settle at the logical threshold of the inverter ideally at VDD/2.
Q2. The Vt of the transistor increases or decreases with the temperature.
Ans. The Vt of the the transistor decreases with temperature?
Q3. According to the saturation current equation the current through the transistor increases as Vt of the transistor decreases but it is not the case in practical situation, the reason is ?
Ans. The reason is the mobility of the charge carriers as it is the more prominent factor in the ON current equation and it decreases with the temperature.
Q4. What is channel length modulation and how it occurs?
Ans. Channel length modulation is the shortening of the channel length after Pinch off occurs, this causes the saturation current to increase linearly with Vds. This occurs due to the widening of the depletion region between drain to bulk region, primarily in the channel.
Q5. What are short channel effects, is channel length modulation also a short channel effect?
Ans. In short channel technologies, vertical electric field loses its complete control over the channel. That is gate loses its control over the channel as the horizontal electric field starts interfering with the channel formation. The most prominent effects are subthreshold leakage, velocity saturation. No, channel length modulation is not a short channel effect as it occurs after pinch off point, while short channel effects are mostly pre or during channel formation.
Q6. How does a Vt of transistor varies with temperature and doping and why?
Ans. The Vt of the transistor decreases as the temperature increases as minority carrier concentration increases, while Vt of the transistor decreases with increased doping as more majority carriers needs to be pushed into the bulk to create the depletion region before channel formation.
Q7. The value of the capacitance between gate to bulk for an NMOS transistor is maximum in which region of the MOS?
Ans. The gate to bulk capacitance is maximum for the cutoff region of the transistor.
Q8. Considering a 3 terminal NMOS device if a supply of Vdd is connected to the gate of a NOMS having Vt as the threshold value, and the supply voltage of Vdd is connected to either of the remaining terminal, In which of the region does the NMOS is in, and what is the output voltage at the remaining terminal?
Ans. The transistor being an NMOS works in saturation region, and being an NMOS its weak pull up, the output voltage will be Vdd-Vt.
Q9. Considering the question above if we connect another NMOS with its drain connected to the output of the previous NMOS and gate being connected to Vdd, then in which region does this NMOS operates in and what is the output voltage?
Ans. The transistor works in saturation region, the output voltage will be Vdd-Vt. The first transistor is connected to Vdd which make it’s Vds as Vdd -(Vdd-Vt) which is greater than Vgs-Vt, for the second transistor it can pass the voltage level up to which Vgs = Vt, this means it can also pass the full Vdd – Vt potential which is at its drain, also here Vds = Vgs – Vt, so it also works in saturation region.
Q10. If the voltage Vsb that is source to bulk voltage difference is increased in an NMOS how does Vt varies and why?
Ans. The Vt of the transistor increases, as the depletion region around the p-n junction increases and it takes more gate voltage to offset that charge.