The next stop in our journey of Interview Question Banks is that of LG Electronics. To help you in your preparation for LG Electronics and similar companies in the same domain, we have collected questions asked in their interviews from various sources at one place. Let’s start with them…
Q : What is setup and hold time?
A : Setup time is the amount of time before the active edge of clock during which data should remain stable. Hold time is the (minimum) time after the active edge of the clock during which the data must be held stable.
Q : What do you mean by latch-up?
A : Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic SCR – Silicon Controlled Rectifier) is inadvertently created within a circuit. This causes a high amount of current to continuously flow through it once it is accidentally triggered or turned on. The amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS) depending on the circuits involved.
Q : What do you mean by Noise Margin? How is it calculated?
A : It is the maximum amount of noise that can be added on the input stage and still get the desired output. It is of two types,
Noise Margin (High), NMH = VOH – VIH
Noise Margin (Low), NML = VIL – VOL
The net Noise Margin is calculated as min(NMH,NML).
Q : Which among NAND and NOR is preferred for fabrication & why?
A : NAND is a preferred choice for design than NOR because at the transistor level, the mobility of electrons is greater than that of holes (normally three times) compared to NOR and thus the NAND is a faster gate. Also, NAND circuits have lower gate leakage than NOR which means that high-to-low delay (tphl) and low-to-high delay (tplh) are more symmetric in NAND. In NOR, tplh is higher (as PMOS are in series connection which increases resistance) than tphl.
Q : What is the time constant for differentiator and integrator?
A : Time constant (=RC) for a differentiator should be small and that of integrator, should be large.
Q : What is meant by sizing of the inverter?
A : Sizing of inverter means to modify (w/L) of transistors to achieve optimum output. The size (width) of the inverters need to be increased in order to drive desired load capacitance for obtaining an optimized performance.
(Continued to Part 2…)