Category: Verilog

Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog. Blocking Assignments Nonblocking Assignments To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Blocking assignments (=) are done sequentially in the order the statements are written. A second…

Delay in Assignment (#) in Verilog

Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment…

Synthesis and Functioning of Blocking and Non-Blocking Assignments.

Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. They are procedural assignments always used in a procedural block…

Port Mapping for Module Instantiation in Verilog

Port mapping in module instantiation can be done in two different ways: Port mapping by order Port mapping by name In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows…

Module Instantiation in Verilog

A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating…

Ports in Verilog Module

Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All…

Module Definition in Verilog

A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but…

Different Coding Styles of Verilog Language

Verilog language has the capability of designing a module in several coding styles. Depending on the needs of a design, internals of each module can be defined at four level of abstractions. Irrespective of the internal abstraction level, the module…

Synopsys – Interview Questions – based on Synthesis and Simulation

This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself…

Case and Conditional Statements Synthesis CAUTION !!!

Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by…