Category: DHD

Digital Hardware Design

Step by Step Method to Design a Combinational Circuit

The Electronics engineers should know the steps to design a particular circuit. While we study, we directly study the properties of the electronic block and the circuit diagram of the corresponding block. We never think how had we landed up to that…

Getting started with TLM 2.0 – Introduction and Basic Constructs

The TLM 2.0 transaction level modeling standard from the Open SystemC Initiative (OSCI) was released on 9th June 2008. Transaction-level modeling (TLM) is a high-level modern approach to modeling digital systems. That modeling is based on the abstraction of the…

What is TLM-1 and what was the need for TLM 2.0?

Transaction-level modeling (TLM) is a high-level modern approach for modeling digital systems. TLM-1 standard defined a set of interfaces which could be used for transporting transaction by value or reference. TLM-1 is being used successfully in some applications but it…

SETUP Time and SETUP Violation in a Single D Latch

Setup and Hold time concept is one of the fundamental concepts that is very necessary for closing and analysing and timing margin. The analysis in digital domain, in Reg to Reg system is very popular but the root cause of…

Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog. Blocking Assignments Nonblocking Assignments To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Blocking assignments (=) are done sequentially in the order the statements are written. A second…

Delay in Assignment (#) in Verilog

Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment…

Synthesis and Functioning of Blocking and Non-Blocking Assignments.

Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. They are procedural assignments always used in a procedural block…

FPGA vs. Microcontroller

FPGA stands for Field Programmable Gate Array. They are programmable integrated circuits made up of a large number configurable logic blocks (CLBs), fixed function blocks and memory blocks which can be used to perform complex digital computations. The CLBs are…

Digital Design Methodologies

—There are two basic types of digital design methodologies: top-down design methodology bottom-up design methodology. top-down Design Methodology —In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further…

Port Mapping for Module Instantiation in Verilog

Port mapping in module instantiation can be done in two different ways: Port mapping by order Port mapping by name In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows…