Author: Sidhartha

Fault Tolerance Measures

Fault tolerance of electronic system is a major concern for the VLSI engineers. This can be realized from the post Need of Fault Tolerant VLSI System Design. The objective of this post is to introduce the proper tools for fault…

Defects, Errors, and Faults

In Electronics industry incorrectness in products are described in several ways which may create confusion in understanding the terms defect, error and fault. Though these terms are used interchangeably in the field of VLSI testing, let’s try to draw a…

Redundancy in Fault Tolerance

In the previous post we have understood the need of Fault Tolerance in VLSI System Design. A VLSI system can broadly be considered as a union of following 3 layers: Hardware Layer (Processing cores, Memories, etc.) Software Layer (OS, Program…

Need of Fault Tolerant VLSI System Design

In recent few years VLSI design has achieved remarkable growth. High performance (peta-scale) computing is a reality now and we are expecting exa-scale computing by 2020. We talk about many core processor now a days. Intel’s Xeon Phi (Knights Landing)…

Delay in Assignment (#) in Verilog

Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment…

Digital Design Methodologies

There are two basic types of digital design methodologies: top-down design methodology bottom-up design methodology. top-down Design Methodology In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further…