Modern day Syetem-on-Chips are so complex that pre-silicon verification is no more the sufficient step to capture all the design bugs. Even with sophisticated verification process, achieving 100% coverage is difficult. Due to this, few bugs escape from the pre-silicon…
Author: Sidhartha
Pre-Silicon Verification vs. Post-Silicon Validation
Both Verification and Validation checks for the correctness of the design. These design steps try to detect and localize functional bugs in the system. While pre-silicon verification runs the test cases on the software prototypes of the design on the…
Resistive Divider Circuit
Resistive divider circuit can alternatively be called as voltage divider circuit. Such a circuit is shown in the following figure: This circuit divides the input voltage Vin depending on the resistance values according to the following formula: Vout = Vin…
Resistive Divider Layout Simulation
Now we are ready to simulate the layout view off this cell. Let’s open up the schematic view of the cell and copy the SPICE code. Go back to the layout view and paste the SPICE code. Increase the text…
Resistive Divider Layout
Open the layout view of the Resistive_divider cell and then copy/paste (Ctrl+C/Ctrl+V) an additional resistor. Running a DRC (pressing F5) on the above layout results in the following error. By pressing > we see that there is too little space…
Resistive Divider Schematic Simulation
Now we would simulate the resistive divider circuit which has been built, and would observe the output voltage w.r.t. a particular input voltage. For this we need to write a SPICE code which would give the description of the input…
Resistive Divider Schematic
Before starting the schematic design let’s celebrate the fact that the most commonly used following shortcuts in our daily life are also valid for Electric VLSI. Now we would build a resistive divider circuit. Go to the schematic view of…
Setup of LTspice with Electric
LTspice is a free software which performs SPICE simulations for electronic circuits. We use LTspice for spice simulation of the circuit designed in Electric. Setting in Electric Following are the steps to be followed to set up LTspice with Electric:…
Checking ERC (Well Check)
This process checks the connection of the n-well and p-substrate. The C5 process used here is an n-well process. The p-type substrate is common to all NMOS devices and should be grounded. One of the electrical rule checks (ERCs) is…
Layout vs. Schematic (LVS)
Layout vs. Schematic (LVS) in Electric is checked using Network Consistency Checking (NCC) To check this, execute Tools –> NCC –> Schematic and Layout views of Cell in Current Window. You can run this command being in any design window (schematic…